| Info hash | 53bae6d22f3b6e692673f9335e0a0198c1618426 |
| Last mirror activity | 21d,18:56:11 ago |
| Size | 5.56GB (5,558,550,001 bytes) |
| Added | 2016-09-26 15:54:59 |
| Views | 2162 |
| Hits | 7914 |
| ID | 3432 |
| Type | multi |
| Downloaded | 25003 time(s) |
| Uploaded by |  joecohen |
| Folder | coursera-comp-arch |
| Num files | 121 files [See full list] |
| Mirrors | 13 complete, 0 downloading = 13 mirror(s) total [Log in to see full list] |
coursera-comp-arch (121 files)
 assigments/assigment1/PS1.pdf |
129.15kB |
| assigments/assigment1/PS1_Solutions_Small.pdf |
1.77MB |
| assigments/assigment1/PS1A.pdf |
817.26kB |
| assigments/assigment2/PS2.pdf |
140.30kB |
| assigments/assigment2/PS2_Solutions_Small.pdf |
807.17kB |
| assigments/assigment3/PS3.pdf |
178.60kB |
| assigments/assigment3/PS3_Solutions.pdf |
133.84kB |
| assigments/assigment4/PS4.pdf |
167.16kB |
| assigments/assigment4/PS4_Solutions_Small.pdf |
366.68kB |
| assigments/assigment4/PS4A.pdf |
256.14kB |
| assigments/assigment5/PS5.pdf |
179.24kB |
| assigments/assigment5/PS5_Solutions.pdf |
888.57kB |
| assigments/assigment5/PS5A.pdf |
564.75kB |
| lectures/01-Introduction/Computer Architecture 0.0 L00-S1Course Introduction.mp4 |
104.24MB |
| lectures/02-Instruction-Set-Architecture-Microcode/Computer Architecture 1.0 L1S1 Course Overview (434).mp4 |
19.04MB |
| lectures/02-Instruction-Set-Architecture-Microcode/Computer Architecture 1.1 L1S2 Motivation (1640).mp4 |
99.66MB |
| lectures/02-Instruction-Set-Architecture-Microcode/Computer Architecture 1.2 L1S3 Course Content (910).mp4 |
27.00MB |
| lectures/02-Instruction-Set-Architecture-Microcode/Computer Architecture 1.3 L1S4 Architecture and Microarchitecture (2337).mp4 |
55.40MB |
| lectures/02-Instruction-Set-Architecture-Microcode/Computer Architecture 1.4 L1S5 Machine Models (1602).mp4 |
34.43MB |
| lectures/02-Instruction-Set-Architecture-Microcode/Computer Architecture 1.5 L1S6 ISA Characteristics (2547).mp4 |
60.84MB |
| lectures/02-Instruction-Set-Architecture-Microcode/Computer Architecture 1.6 L1S7 Recap (0117).mp4 |
2.02MB |
| lectures/03-Pipelining-Review/Computer Architecture 2.0 L2S1 Microcoded Microarchitecture (1408).mp4 |
85.84MB |
| lectures/03-Pipelining-Review/Computer Architecture 2.1 L2S2 Pipeline Basics (3051).mp4 |
67.84MB |
| lectures/03-Pipelining-Review/Computer Architecture 2.2 L2S3 Structural Hazard (1013).mp4 |
24.29MB |
| lectures/03-Pipelining-Review/Computer Architecture 2.3 L2S4 Data Hazards (4633).mp4 |
97.45MB |
| lectures/04-Cache-Review/Computer Architecture 3.0 L3S1 Control Hazards Jumps (1556).mp4 |
28.25MB |
| lectures/04-Cache-Review/Computer Architecture 3.1 L3S2 Control Hazards Branch (2402).mp4 |
49.82MB |
| lectures/04-Cache-Review/Computer Architecture 3.2 L3S3 Control Hazards Others(751).mp4 |
16.35MB |
| lectures/04-Cache-Review/Computer Architecture 3.3 L3S4 Memory Technologies (2247).mp4 |
52.95MB |
| lectures/04-Cache-Review/Computer Architecture 3.4 L3S5 Motivation for Caches (2225).mp4 |
133.55MB |
| lectures/05-Superscalar1/Computer Architecture 4.0 L4S1 Classifying Caches (2807).mp4 |
167.47MB |
| lectures/05-Superscalar1/Computer Architecture 4.1 L4S2 Cache Performance (1711).mp4 |
32.80MB |
| lectures/05-Superscalar1/Computer Architecture 4.2 L4S3 Superscalar 1 (642).mp4 |
14.12MB |
| lectures/05-Superscalar1/Computer Architecture 4.3 L4S4 Basic Two-way In-order Superscalar (456).mp4 |
9.94MB |
| lectures/05-Superscalar1/Computer Architecture 4.4 L4S5 Fetch Logic and Alignment (1101).mp4 |
20.05MB |
| lectures/06-Superscalar3-and-Exceptions/Computer Architecture 5.0 L5S1 Baseline Superscalar and Alignment (416).mp4 |
8.90MB |
| lectures/06-Superscalar3-and-Exceptions/Computer Architecture 5.1 L5S2 Interrupts and Bypassing (1213).mp4 |
24.81MB |
| lectures/06-Superscalar3-and-Exceptions/Computer Architecture 5.2 L5S3 Interrupts and Exceptions (2925).mp4 |
60.01MB |
| lectures/06-Superscalar3-and-Exceptions/Computer Architecture 5.3 L5S4 Introduction to Out-of-Order Processors (3053).mp4 |
64.93MB |
| lectures/07-Superscalar3/Computer Architecture 6.0 L6S1 Review of Out-of-Order Processors (326).mp4 |
7.19MB |
| lectures/07-Superscalar3/Computer Architecture 6.1 L6S2 I2O2 Processors (1958).mp4 |
40.68MB |
| lectures/07-Superscalar3/Computer Architecture 6.2 L6S3 I2O1 Processors (2844).mp4 |
169.75MB |
| lectures/07-Superscalar3/Computer Architecture 6.3 L6S4 IO3 Processors (1623).mp4 |
33.56MB |
| lectures/07-Superscalar3/Computer Architecture 6.4 L6S5 IO2I Processors (431).mp4 |
8.46MB |
| lectures/08-Superscalar4/Computer Architecture 7.0 L7S1 Speculation and Branch (1437).mp4 |
30.49MB |
| lectures/08-Superscalar4/Computer Architecture 7.1 L7S2 Register Renaming Introduction (1108).mp4 |
66.37MB |
| lectures/08-Superscalar4/Computer Architecture 7.2 L7S3 Register Renaming with Pointers to IQ and ROB (2454).mp4 |
148.66MB |
| lectures/08-Superscalar4/Computer Architecture 7.3 L7S4 Register Renaming with Values in IQ and ROB (1214).mp4 |
70.87MB |
| lectures/08-Superscalar4/Computer Architecture 7.4 L7S5 Memory Disambiguation (949).mp4 |
58.63MB |
|
|
|
Type: Course
Tags:
Bibtex:
Tags:
Bibtex:
@article{,
title= {[Coursera] Computer Architecture },
keywords= {},
journal= {},
author= {David Wentzlaff (Princeton University)},
year= {},
url= {},
license= {},
abstract= {About this course: In this course, you will learn to design the computer architecture of complex modern microprocessors.
### Introduction, Instruction Set Architecture, and Microcode
This lecture will give you a broad overview of the course, as well as the description of architecture, micro-architecture and instruction set architectures.
### Pipelining Review
This lecture covers the basic concept of pipeline and two different types of hazards.
### Cache Review
This lecture covers control hazards and the motivation for caches.
### Superscalar 1
This lecture covers cache characteristics and basic superscalar architecture.
### Superscalar 2 & Exceptions
This lecture covers the common issues for superscalar architecture.
### Superscalar 3
This lecture covers different kinds of architectures for out-of-order processors.
### Superscalar 4
This lecture covers the common methods used to improve the performance of out-of-order processors including register renaming and memory disambiguation.
### VLIW 1
This lecture covers the basic concept of very long instruction word (VLIW) processors.
### VLIW2
This lecture covers the common methods used to improve VLIW performance.
### Branch Prediction
This lecture covers the motivation and implementation of branch predictors.
### Advanced Caches 1
This lecture covers the advanced mechanisms used to improve cache performance.
### Advanced Caches 2
This lecture covers more advanced mechanisms used to improve cache performance.
### Memory Protection
This lecture covers memory management and protection.
### Vector Processors and GPUs
This lecture covers the vector processor and optimizations for vector processors.
### Multithreading
This lecture covers different types of multithreading.
### Parallel Programming 1
This lecture covers the concepts of parallelism, consistency models, and basic parallel programming techniques.
### Parallel Programming 2
This lecture covers the solutions for the consistency problem in parallel programming.
### Small Multiprocessors
This lecture covers the implementation of small multiprocessors.
### Multiprocessor Interconnect 1
This lecture covers the design of interconnects for a multiprocessor.
### Multiprocessor Interconnect 2
This lecture covers the design of interconnects for multiprocessor and network topology.
### Large Multiprocessors (Directory Protocols)
This lecture covers the motivation and implementation of directory protocol used for coherence on large multiproccesors.
},
superseded= {},
terms= {}
}
